1. Field of the Invention
The present invention relates to an apparatus for reproducing information that has been written on a storage medium such as an optical disk or a magnetic disk.
2. Description of the Related Art
Recently, various types of digital information storage devices (e.g., hard disk drive (HDD), optical disk drive and magneto-optical disk drive) have been used extensively in audiovisual appliances, personal computers and video tape recorders (VTRs) with a built-in digital recording camera, for example. These storage devices are now required to further increase the storage capacity. To increase the storage capacity, data should be recorded at a sufficiently high density on a storage medium such as hard disk, optical disk or magneto-optical disk, and the data recorded should be read accurately enough.
Among various high-density signal recording/processing techniques, a partial response maximum likelihood (PRML) method is known as a technique that has been highly developed particularly in the field of HDDs. See Osawa, Okamoto and Saito, “Signal Processing Technology for High-Density Digital Magnetic Recording”, Shingakuron C-II, Vol. J81-C-II, No. 4, pp. 393-412 (April 1998), for example. In the PRML method, data is written or read onto/from a storage medium while taking intersymbol interference, which occurs if the data has been recorded thereon at a high density, into account. More specifically, in reproducing information, digital data, or a version of the signal that has been partial-response equalized with a predetermined frequency characteristic using an equalizer, for example, is produced and then this signal is decoded into most likely (or most probable) digitized data (i.e., binary data) by a Viterbi decoding technique, for example. In this manner, data can be decoded at a low error rate even from a read signal with a low signal-to-noise ratio (SNR) or with a relatively high level of jitter resulting from intersymbol interference.
Hereinafter, a magnetic disk drive (i.e., HDD) that utilizes the conventional PRML method will be described with reference to FIG. 8. To reproduce digital information that has been recorded on a magnetic disk 11, the magnetic disk drive 200 includes magnetic head 12, automatic gain controller (AGC) 3, waveform equalizer (EQ1) 40, clock generator 6, analog-to-digital converter (ADC) 8 and PRML circuit 10.
A signal, which has been read out by the magnetic head 12 from the magnetic disk 11, has its amplitude controlled to a predetermined level by the AGC 3. Next, the amplitude-controlled signal has its waveform shaped by the waveform equalizer 40 so that the high-frequency components thereof are boosted. Then, the output signal 141 of the waveform equalizer 40 is input to both of the ADC 8 and the clock generator 6.
The clock generator 6 includes a phase-locked loop (PLL) circuit and generates a clock signal using a voltage-controlled oscillator (VCO). As will be described later, the clock signal generated has its phase controlled by a phase shifter 7 and then output to the ADC 8.
In response to the clock signal that has been received from the phase shifter 7, the ADC 8 samples the output signal 141 of the waveform equalizer 40, thereby generating a digital signal (or digital samples) 81. The digital signal 81 output from the ADC 8 has a value falling within a limited range. For example, where the resolution is 8 bits, the digital signal 81 can represent a value of 0 to 255 according to the decimal notation.
The digital signal 81 obtained in this manner is input to the PRML circuit 10 and a phase control signal generator 9. The phase control signal generator 9 is provided to appropriately control the phase of the clock signal 61. Specifically, responsive to the digital signal 81 received, the phase control signal generator 9 generates a phase control signal 91 and outputs the signal 91 to the phase shifter 7. A more detailed configuration of the phase control signal generator 9 is described in Japanese Laid-Open Publication No. 10-228733, for example.
The PRML circuit 10 includes a digital equalizer 10a and a most likelihood (ML) detector 10b such as a Viterbi decoder. The digital signal 81, which has been input to the PRML circuit 10, is equalized by the digital equalizer 10a to have a predetermined PR characteristic and then decoded into digitized data by the ML detector 10b. In this manner, the PRML circuit 10 can reproduce data accurately enough even from a signal with a relatively high level of jitter resulting from the intersymbol interference.
Next, the waveform equalizer 40 will be described in further detail with reference to FIG. 9. As shown in FIG. 9, the waveform equalizer 40 includes delay circuits 42a and 42b, amplifiers 43a and 43b and adder 44, and operates in such a manner as to amplify the high-frequency band of its input signal. Thus, the waveform equalizer 40 can amplify a signal corresponding to a recording pattern in which a number of transitions occur successively within a short period of time (i.e., a signal with a high frequency). The waveform equalizer 40 can reduce unwanted effects of the intersymbol interference on such a signal pattern and suppress the jitter.
As shown in FIG. 8, the output signal 141 of the waveform equalizer 40 is converted by the ADC 8 into digital data, which is then decoded by the PRML circuit 10. The digital data is also used to get a read clock signal extracted by the clock generator 6. In any of these circuits, a signal should preferably have its high-frequency components amplified to a certain degree and have its jitter reduced.
The PRML circuit 10 decodes the digitized data from the sampled data. By getting the high-frequency components of a signal amplified in advance by the waveform equalizer 40, the ADC 8 can sample such signal components at a sufficiently high quantization precision. The clock generator 6 extracts the read clock signal from the read signal. In this case, the clock generator 6 can also generate the read clock signal more appropriately if the read signal has had its high-frequency components amplified and if the jitter on the read signal is reduced.
In this manner, by subjecting the signal that will be input to the PRML circuit 10 and clock generator 6 to the equalization processing in advance using the waveform equalizer 40, information can be reproduced more accurately.
However, if data is recorded at an even higher density, the unwanted effects of the intersymbol interference further increase. Then, it is even more difficult to read a signal accurately enough. To realize a higher-density recording operation in the field of optical disk drives, in particular, a reproducing apparatus such as that illustrated in FIG. 8 might sometimes be unable to reduce the error rate sufficiently.
On an optical disk, for example, digital information is recorded as marks and spaces. Generally speaking, a shorter mark (or space) is recognized as a signal with smaller amplitude. To identify a signal like this (i.e., a high-frequency signal with a small intensity) accurately, the waveform equalizer 40 should have its equalization characteristics controlled appropriately. For the reproducing apparatus shown in FIG. 8, however, it is not easy to control and optimize the equalization characteristics of the waveform equalizer 40 so that a signal can be read accurately enough. Hereinafter, the reasons will be described in further detail.
Where the PRML decoding technique is adopted as in the foregoing example, a read signal should be A/D converted by sampling the signal once a channel bit period. However, to obtain an intended sampling clock signal corresponding to the channel bit period, the read signal should have its jitter reduced sufficiently before supplied to the clock generator. This is because if the read signal has a jitter of a non-negligible level, then the clock generator 6 cannot extract the desired read clock signal.
Furthermore, if the storage medium is a removable one such as an optical disk, it is even more difficult to generate the read clock signal as intended. This is because data may be written or read on/from an optical disk using mutually different drives. Accordingly, when a signal is read out from the disk, the read signal might have wow (i.e., a small variation in transfer rate). To generate a clock signal from such a read signal with wow, the PLL circuit should have a gain high enough to follow up the read signal. However, where the gain of the PLL circuit has been increased, a read signal with a non-negligible jitter will cause a bit slip error. In that case, even if the read signal is subjected to the PRML processing after that, non-correctible errors should occur.
Accordingly, to generate the intended clock signal, the read signal should preferably be subjected to the waveform equalization in such a manner as to have its jitter minimized.
However, if the equalization characteristics of the waveform equalizer 40 are optimized (e.g., by controlling the equalization level K of the amplifiers 43a and 43b in the equalizer 40) for the jitter reduction purpose, then the resultant equalization characteristics will not match the PRML method, thus possibly increasing the error rate unintentionally. In the PRML decoding method, the read signal that will be input to the ML detector should preferably be equalized so that the read/write signal processing system, including the storage medium such as an optical disk, has its frequency response characteristic adapted to the predetermined partial response. Accordingly, if the equalization characteristics of the equalizer 40 do not match the desired PR equalization, it is difficult to read the signal accurately. That is to say, appropriate equalization characteristics should be selected for the equalizer 40 so that the equalization characteristics are compatible with the predetermined PRML decoding method and that the jitter of the read signal can be reduced.
Also, in obtaining phase deviation information of the sampling clock signal from the digital read signal, the phase control signal generator 9 measures an unwanted phase deviation of the sampling clock signal by the amplitude level of the digital read signal. In this case, if the waveform equalizer 40 has too small an equalization level K, then the phase deviation detected when a short mark is read becomes different from the phase deviation detected when a long mark is read even though these phase deviations are actually equal to each other. Accordingly, the equalization level K of the waveform equalizer 40 needs to be increased to a certain degree. However, if the equalization level K is increased excessively, then the intersymbol interference rather increases and the PR equalization cannot be carried out as intended later.
As described above, in the conventional information reproducing apparatus, appropriate equalization characteristics should be selected for the waveform equalizer in view of a number of considerations including intended clock signal generation and accurate information signal decoding. Thus, as the recording density is further increased, it becomes more and more difficult to make the best selection for an optical disk drive, in particular.